Difference between revisions of "Agnus"
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=== Specifications === | === Specifications === | ||
| − | Agnus provides a | + | Agnus provides a DMA controller, address generator and video sync signals. 25 DMA channels are available which control functions for memory refresh, blitter, bitplanes, "Copper" co-processor, sprites, audio and disk drive. The address generator provides a bus which all three custom chips share, the Register Address Bus. The video sync signals are buffered and may be used for an RGB monitor, composite video or timing for the two CIA chips. |
=== Pinout === | === Pinout === | ||
Revision as of 02:17, 7 February 2023
History
The heart of the Amiga, Agnus was designed by Jay Miner, Joe Decuir, Ron Nicholson, Edwin Chu and Dave Needle. The chip’s architecture remained relatively unchanged throughout development aside from the ability to address 512K of RAM and the addition of a line draw circuit, which was suggested by Dale Luck.
Early versions of the chip are also known as 4701.
Specifications
Agnus provides a DMA controller, address generator and video sync signals. 25 DMA channels are available which control functions for memory refresh, blitter, bitplanes, "Copper" co-processor, sprites, audio and disk drive. The address generator provides a bus which all three custom chips share, the Register Address Bus. The video sync signals are buffered and may be used for an RGB monitor, composite video or timing for the two CIA chips.
Pinout
1 D8
2 D7
3 D6
4 D5
5 D4
6 D3
7 D2
8 D1
9 D0
10 VCC
11 /RES
12 /INT3
13 DMAL
14 /BLS
15 /DBR
16 /ARW
17 RGA8
18 RGA7
19 RGA6
20 RGA5
21 RGA4
22 RGA3
23 RGA2
24 RGA1
25 CCK
26 CCKQ
27 VSS
28 DRA0
29 DRA1
30 DRA2
31 DRA3
32 DRA4
33 DRA5
34 DRA6
35 DRA7
36 DRA8
37 /LP
38 /VSY
39 /CSY
40 /HSY
41 VSS
42 D15
43 D14
44 D13
45 D12
46 D11
47 D10
48 D9
