Agnus
History
The heart of the Amiga, Agnus was designed by Jay Miner, Joe Decuir, Ron Nicholson, Edwin Chu and Dave Needle. The chip’s line draw feature was suggested by Dale Luck and implemented by Dave Needle shortly before the 1984 Winter CES in Las Vegas, where the Lorraine was first shown.
Early versions of the chip are also known as 4701.
Specifications
Agnus provides a DMA controller, address generator and video sync signals. 25 DMA channels are control functions for memory refresh, blitter, bitplanes, "Copper" co-processor, sprites, audio and disk drive. The address generator provides a bus which all three custom chips share, the Register Address Bus. Horizonal, vertical and composite sync signals are available and can be used for an RGB monitor, genlock, composite video or TOD clocks for the two CIA chips.
Versions
| Model No. | Region | Hardware |
|---|---|---|
| 4701 | NTSC | ICS |
| 8361 | NTSC | OCS |
| 8367 | PAL | OCS |
| 8370 | NTSC | ECS |
| 8371 | PAL | ECS |
| 8372 | PAL | ECS |
| 8372A | PAL | ECS |
| 8372AB | PAL | ECS |
| 8372B | NTSC | ECS |
| 8375 | NTSC | ECS |
| 8375 | PAL | ECS |
Pinout (OCS versions)
1 D8
2 D7
3 D6
4 D5
5 D4
6 D3
7 D2
8 D1
9 D0
10 VCC
11 /RES
12 /INT3
13 DMAL
14 /BLS
15 /DBR
16 /ARW
17 RGA8
18 RGA7
19 RGA6
20 RGA5
21 RGA4
22 RGA3
23 RGA2
24 RGA1
25 CCK
26 CCKQ
27 VSS
28 DRA0
29 DRA1
30 DRA2
31 DRA3
32 DRA4
33 DRA5
34 DRA6
35 DRA7
36 DRA8
37 /LP
38 /VSY
39 /CSY
40 /HSY
41 VSS
42 D15
43 D14
44 D13
45 D12
46 D11
47 D10
48 D9
References
- Peck, Rob. Amiga Hardware Manual 1985
- Agnus Big Book of Amiga Hardware
- Caufield, Nicola and Anthony, directors. From Bedrooms to Billions: The Amiga Years. Rebellion, 2015
