Appendices

Appendix A - REGISTER BITS

APPENDIX A - Commodore-Amiga PC Hardware Manual

THIS IS THE SYSTEM FILE NAMED "REGBITS".
It is generated and maintained by Commodore-Amiga Hardware Engineering.

REVISION .5 (DEC 04, 1984)

ADKCON	4F	W	P	Audio, Disk, Control write
ADKCONR	*08	R	P	Audio, Disk, Control read

BIT #	USE
15	SET/CLR	Set/Clear control bit. Determines if bits written with a 1 get set or cleared. Bits written with a zero are always unchanged.
14-13	PRECOMP 1-0	00 = none, 01 = 140ns, 10 = 280 ns, 11 = 560 ns
12	MFMPREC	(1 = MFM precomp, 0 = GCR precomp)
11	UARTBRK	Forces a UART break (clears TXD) if true
10	WORDSYNC	Enables disk read synchronizing on a word equal to DISK SYNC CODE, located in address (3F) * 2
09	MSBSYNC	Enables disk read synchronizing on the MSB (most signif. bit) Apple type GCR
08	FAST	Disk data clock rate control: 1 = fast (2 us) 0 = slow (4us), (fast for MFM, slow for MFM or GCR)
07	USE3PN	Use audio channel 3 to modulate nothing
06	USE2PN	Use audio channel 2 to modulate period of channel 3
05	USE1PN	Use audio channel 1 to modulate period of channel 2
04	USE0PN	Use audio channel 0 to modulate period of channel 1
03	USE3VN	Use audio channel 3 to modulate nothing
02	USE2VN	Use audio channel 2 to modulate volume of channel 3
01	USE1VN	Use audio channel 1 to modulate volume of channel 2
00	USE0VN	Use audio channel 0 to modulate volume of channel 1

NOTE If both period and volume are modulated on the same channel, the period and volume will be alternated.

First word xxxxxxxx V7-V0, Second word P15-P0 (etc)

AUDxLCH	+ 50	W	A	Audio channel x location (High 3 bits)
AUDxLCL	+ 51	W	A	Audio channel x location (Low 15 bits)

This pair of registers contain the 18 bit starting address (location) of Audio channel x (x = 0,1,2,3) DMA data. This is not a pointer register and therefore only needs to be reloaded if a different memory location is to be output.

AUDxLEN	52	W	P	Audio channel x length

This register contains the length (number of words) of Audio channel DMA data.

AUDxPER	53	W	P	Audio channel x period

This register contains the period (rate) Audio channel x DMA data transfer.

AUDxVOL	54	W	P	Audio channel x volume

This register contains the volume setting for Audio channel x. Bits 6,5,4,3,2,1,0 specify 65 linear volume levels as shown below.

BITS	USE
15-07	Not used
06	Forces volume to max (64 ones, no zeros)
05-00	Sets one of 64 levels (000000 = no output), (111111 = 63 ones, one zero)

AUDxDAT	&55	W	A	Audio channel x Data

This register is the audio channel x (x = 0,1,2,3) DMA data buffer. It contains 2 bytes of data that are output sequentially (with digital to analog conversion) to the audio output pins. The DMA controller automatically transfers data to this register from RAM. The processor can also write directly to this register. When the DMA data is finished (words output=length) and the data in this register has been used, an audio channel interrupt request is set.

BLTxPTH	+ *28	W	A	Blitter Pointer to x (High 3 bits)
BLTxPTL	+ *29	W	A	Blitter Pointer to x (Low 15 bits)

This pair of registers contains the 18 bit address of Blitter source (x = A,B,C) or dest. (x = D) DMA data. This pointer must be preloaded with the starting address of the data to be processed by the Blitter. After the Blitter is finished it will contain the last data address (plus increment and modulo).

BLTxMOD	*32	W	A	Blitter Modulo x

This register contains the Modulo for Blitter source (x = A,B,C) or dest (x = D). A Modulo is a number that is automatically added to the address at the end of each line, in order that the address then points to the start of the next line. Each source or destination has its own Modulo, allowing each to be a different size, while an identical area of each is used in the Blitter operation.

BLTAFWM	*22	W	A	first word mask for source A
BLTALWM	*23	W	A	last word mask for source A

The patterns in these two registers are "ANDed" with the first and last words of each line of data from source A into the Blitter. A zero in any bit overrides the data from source A. These registers should be set to all "ones" for fill mode or for line drawing mode.

BLTxDAT	*3A	W	A	Blitter source x data reg.

This register hold source x (x = A,B,C) data for use by the Blitter. It is normally loaded by the Blitter DMA channel, however it may also be preloaded by the microprocessor.

BLTDDAT	Blitter destination data register

This register holds the data resulting from each word of Blitter operation until it is sent to a RAM destination. This is a dummy address and cannot be read by the micro. The transfer is automatic during Blitter operation.

BLTCON0	*20	W	A	Blitter control register 0
BLTCON1	*21	W	A	Blitter control register 1

These two control registers are used together to control Blitter operations. There are 2 basic modes, area and line, which are selected by bit 0 of BLTCON1, as shown below.

AREA MODE (“normal”)	(“)	(“)	LINE MODE (line draw)	(“)	(“)
BIT #	BLTCON0	BLTCON1	BIT#	BLTCON0	BLTCON1
15	ASH3	BSH3	15	ASH3	BSH3
14	ASH2	BSH2	14	ASH2	BSH2
13	ASH1	BSH1	13	ASH1	BSH1
12	ASH0	BSH0	12	ASH0	BSH0
11	USEA	X	11	1	X
10	USEB	X	10	0	X
09	USEC	X	09	1	X
08	USED	X	08	1	X
07	LF7	X	07	LF7	X
06	LF6	X	06	LF6	SIGN
05	LF5	X	05	LF5	OVF
04	LF4	EFE	04	LF4	SUD
03	LF3	IEE	03	LF3	SUL
02	LF2	FCI	02	LF2	AUL
01	LF1	DESC	01	LF1	SING
00	LF0	LINE (= 0)	00	LF0	LINE (= 1)

ASH3 = 0 Shift value of A source
BSH3 = 0 Shift value of B source and line texture
USEA Mode control bit to use Source A
USEB Mode control bit to use Source B
USEC Mode control bit to use Source C
USED Mode control bit to use Source D
LF7-0 Logic function minterm select lines
EFE Exclusive fill enable
IFE Inclusive fill enable
FCI Fill carry input
DESC Descending (decreasing address) control bit
LINE Line mode control bit
SIGN Line draw sign flag
OVF Line draw r/l word overflow flag
SUD Line draw, Sometimes Up or Down (=AUD*)
SUL Line draw, Sometimes Up or Left
AUL Line draw, Always Up or Left
SING Line draw, Single bit per horiz. line

BLTSIZE	* 2C	W	A	Blitter start and size (window width, height)

This register contains the width and height of the Blitter operation (in line mode width must = 2, height = line length). Writing to this register will start the Blitter, and should be done last, after all pointers and control registers have been initialized.

BIT #	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
	h9	h8	h7	h6	h5	h4	h3	h2	h1	h0	w5	w4	w3	w2	w1	w0

h = Height = Vertical lines (10 bits = 1024 lines max)
w = Width = Horiz. pixels (6 bits = 64 words = 1024 pixels max)

BPLxPTH	+70	W	A	Bit-plane x pointer (High 3 bits)
BPLxPTL	+71	W	A	Bit-plane x pointer (Low 15 bits)

This pair of registers contains the 18 bit pointer to the address of bit-plane x (x = 1,2,3,4,5,6) DMA data. This pointer must be reinitialized by the processor or coprocessor to point to the beginning of bit-plane data every vertical blank time.

BPLxDAT	&88	W	D	Bit-plane x data (Parallel to serial convert)

These registers receive the DMA data fetched from RAM by the bit-plane address pointers described above. They act as a 6 word parallel to serial buffer for up to 6 memory "Bit-planes". (x = 3-6)
They are loaded by the display bit-plane DMA controller with data from 6 separate areas of memory. They output to the display most sig. bit first (left to right) simultaneously.

BPL1MOD	84	W	A	Bit-plane modulo (odd planes)
BPL2MOD	85	W	A	Bit-plane modulo (even planes)

These registers contain the Modulos for the odd and even bit-planes. A Modulo is a number that is automatically added to the address at the end of each line, in order that the address then points to the start of the next line. Since they have separate Modulos, the odd and even bit-planes may have sizes that are different from each other, as well as different from the Display Window size

BPLCON0	80	W	A D	Bit-plane control reg. (misc. control bits)
BPLCON1	81	W	D	Bit-plane control reg. (horiz. scroll control)
BPLCON2	82	W	D	Bit-plane control reg. (video priority control)

These registers control the operation of the bit-planes and various aspects of the display.

BIT #	BPLCON0	BPLCON1	BPLCON2
15	HIRES	X	X
14	BPU2	X	X
13	BPU1	X	X
12	BPU0	X	X
11	HOMOD	X	X
10	DBPPF	X	X
09	COLOR	X	X
08	RGB	X	X
07	X	PF2H3	X
06	X	PF2H2	PF2PRI
05	X	PF2H1	PF2P2
04	X	PF2H0	PF2P1
03	LPEN	PH1H3	PF2P0
02	LACE	PH1H2	PF1P2
01	ERSY	PH1H1	PF1P1
00	X	PH1H0	PF1P0

HIRES = High resolution (640) mode
BPU = Bit-plane use code 000-110 (NONE through 6 inclusive)
HOMOD = Hold and Modify mode
DBLPF = Double playfield (PF1 = odd PF2 = even bit-planes)
COLOR = Composite video COLOR enable
RGB = Red/Blue/Green enable bit
LPEN = Light pen enable (reset on power up)
LACE = Interlace enable (reset on power up)
ERSY = External Resync (HSYNC, VSYNC pads become inputs, reset on power up)
PF2PRI = Playfield 2 (even planes) has priority over (appears in front of) Playfield 1 (odd planes)
PF2P = Playfield 2 priority mode (with resp. to sprites)
PF1P = Playfield 1 priority mode (with resp. to sprites)
PF2H = Playfield 2 horizontal scroll code
PF1H = Playfield 1 horizontal scroll code

CLXCON	4C	W	D	Collision control

This register controls which bit-planes are included (enabled)
in collision detection, and their required state if included.
It also controls the individual inclusion of odd numbered
sprites in the collision detection, by logically ORing them
with their corresponding even numbered sprite.

BIT #	FUNCTION	DESCRIPTION
15	ENSP7	Enable Sprite 7 (ORed with Sprite 6)
14	ENSP5	Enable Sprite 5 (ORed with Sprite 4)
13	ENSP3	Enable Sprite 3 (ORed with Sprite 2)
12	ENSP1	Enable Sprite 1 (ORed with Sprite 0)
11	ENBP6	Enable Bit-Plane 6 (Match reqd. for collision
10	ENBP5	Enable Bit-Plane 5 (Match reqd. for collision)
09	ENBP4	Enable Bit-Plane 4 (Match reqd. for collision)
08	ENBP3	Enable Bit-Plane 3 (Match reqd. for collision)
07	ENBP2	Enable Bit-Plane 2 (Match reqd. for collision)
06	ENBP1	Enable Bit-Plane 1 (Match reqd. for collision)
05	MVBP6	Match Value for Bit-Plane 6 collision
04	MVBP5	Match Value for Bit-Plane 5 collision
03	MVBP4	Match Value for Bit-Plane 4 collision
02	MVBP3	Match Value for Bit-Plane 3 collision
01	MVBP2	Match Value for Bit-Plane 2 collision
00	MVBP1	Match Value for Bit-Plane 1 collision

Note: Disabled Bit-Planes cannot prevent collisions. Therefore if all bit-planes are disabled, collisions will be continuous, regardless of the match values.

CLXDAT	*07	R	D	Collision data reg. (Read and clear). This address reads (and clears) the collision detection register. The bit assignments are below.

NOTE: Playfield 1 is all odd numbered enabled bit-planes. Playfield 2 is all even numbered enabled bit-planes.

BIT #	COLLISIONS REGISTERED
15	not used
14	Sprite 4 (or 5) to Sprite 6 (or 7)
13	Sprite 2 (or 3) to Sprite 6 (or 7)
12	Sprite 2 (or 3) to Sprite 4 (or 5)
11	Sprite 0 (or 1) to Sprite 6 (or 7)
10	Sprite 0 (or 1) to Sprite 4 (or 5)
09	Sprite 0 (or 1) to Sprite 2 (or 3)
08	Playfield 2 to Sprite 6 (or 7)
07	Playfield 2 to Sprite 4 (or 5)
06	Playfield 2 to Sprite 2 (or 3)
05	Playfield 2 to Sprite 0 (or 1)
04	Playfield 1 to Sprite 6 (or 7)
03	Playfield 1 to Sprite 4 (or 5)
02	Playfield 1 to Sprite 2 (or 3)
01	Playfield 1 to Sprite 0 (or 1)
00	Playfield 1 to Playfield 2

COLORxx	C0	W	D	Color table xx

There are 32 of these registers (xx = 00-31) and they are sometimes collectively called the "Color Palette". They contain 12-bit codes representing RED, GREEN, BLUE colors for RGB systems. One of these registers at a time is selected (by the BPLxDAT serialized video code) for presentation at the RGB video output pins. The table below shows the color register bit usage.

BIT #	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
RGB	X	X	X	X	R3	R2	R1	R0	G3	G2	G1	G0	B3	B2	B1	B0

B = blue, G = green, R = red
BE = blue enable, GE = green enable, RE = red enable

COPCON	*17	W	A	Coprocessor control register

This is a 1-bit register that when set true, allows the Coprocessor to access the Blitter hardware. This bit is cleared by power on reset, so that the Coprocessor cannot access the Blitter hardware.

BIT #	NAME	FUNCTION
01	CDANG	Coprocessor danger mode. Allows Coprocessor access to Blitter if true.

COPJMP1	44	S	A	Coprocessor restart at first location
COPJMP2	45	S	A	Coprocessor restart at second location

These addresses are strobe addresses, that when written to cause the Coprocessor to jump indirect using the address contained in the First or Second Location registers described below. The Coprocessor itself can write to these addresses, causing its own jump indirect.

COP1LCH	+40	Coprocessor first location reg. (High 3 bits)
COP1LCL	+41	Coprocessor first location reg. (Low 15 bits)
COP2LCH	+42	Coprocessor second location reg. (High 3 bits)
COP2LCL	+43	Coprocessor second location reg. (Low 15 bits)

These registers contain the jump addresses described above.

COPINS	46	W	A	Coprocessor inst. fetch identify

This is a dummy address that is generated by the Coprocessor whenever it is loading instructions into its own instruction register. This actually occurs every Coprocessor cycle except for the second (IR2) cycle of the MOVE instruction. The three types of instructions are shown below.

MOVE Move immediate to dest.

WAIT Wait until beam counter is equal to, or greater than.
(keeps Coprocessor off of bus until beam position has been reached)

SKIP Skip if beam counter is equal to, or greater than.
(skips following MOVE isnt. unless beam position has been reached)

	MOVE	(“)	WAIT UNTIL	(“)	SKIP IF	(“)
BIT #	IR1	IR2	IR1	IR2	IR1	IR2
15	X	RD15	VP7	BFD *	VP7	BFD *
14	X	RD14	VP6	VE6	VP6	VE6
13	X	RD13	VP5	VE5	VP5	VE5
12	X	RD12	VP4	VE4	VP4	VE4
11	X	RD11	VP3	VE3	VP3	VE3
10	X	RD10	VP2	VE2	VP2	VE2
09	X	RD09	VP1	VE1	VP1	VE1
08	DA8	RD08	VP0	VE0	VP0	VE0
07	DA7	RD07	HP8	HE8	HP8	HE8
06	DA6	RD06	HP7	HE7	HP7	HE7
05	DA5	RD05	HP6	HE6	HP6	HE6
04	DA4	RD04	HP5	HE5	HP5	HE5
03	DA3	RD03	HP4	HE4	HP4	HE4
02	DA2	RD02	HP3	HE3	HP3	HE3
01	DA1	RD01	HP2	HE2	HP2	HE2
00	0	RD00	1	0	1	1

IR1 = First instruction register.
IR2 = Second instruction register.
DA = Destination Address for MOVE instruction. Fetched during IR1 time, used during IR2 time on RGA bus.
RD = RAM Data moved by MOVE instruction at IR2 time.
directly from RAM to the address given by the DA field.
VP = Vertical Beam Position comparison bit.
HP = Horizontal Beam Position comparison bit.
VE = Enable comparison (mask bit).
HE = Enable comparison (mask bit).

• NOTE BFD = Blitter Finished Disable. When this bit is true, the Blitter Finished flag will have no effect on the Coprocessor. When this bit is zero, the Blitter Finished flag must be true (in addition to the rest of the bit comparisons) before the Coprocessor can exit from its wait state, or skip over an instruction. Note that the V7 comparison cannot be masked.
  

The Coprocessor is basically a 2 cycle machine that requests the bus only during odd memory cycles. (4 memory cycles per ins.) This prevents collisions with Display, Audio, Disk, Refresh, and Sprites, all of which use only even cycles. It therefore needs (and has) priority over only the Blitter and Micro. There are only three types of instructions, MOVE immediate, WAIT until, and SKIP if. All instructions require 2 bus cycles (and two instruction words). Since only the odd bus cycles are requested, 4 memory cycle times are required per instruction. (memory cycles are 280 ns) There are two indirect jump registers COP1LC and COP2LC. These are 18-bit pointer registers whose contents are used to modify the program counter for initialization or jumps. They are transferred to the program counter whenever strobe addresses COPJMP1 or COPJMP2 are written. In addition, COP1LC is automatically used at the beginning of each vertical blank time. It is important that one of the jump registers be initialized and its jump strobe address hit, after power up but before Coprocessor DMA is initialized. This insures a determined startup address, and state.

DIWSTRT	47	W	A	Display Window Start (upper left vert-hor pos)
DIWSTOP	48	W	A	Display Window Stop (lower right vert-hor pos)

These registers control the Display window size and position by locating the upper left and lower right corners.

BIT #	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
USE	V7	V6	V5	V4	V3	V2	V1	V0	H7	H6	H5	H4	H3	H2	H1	H0

DIWSTRT is vertically restricted to the upper 2/3 of the display (V8 = 0), and horizontally restricted to the left 3/4 of the display (H8 = 0).

DIWSTOP is vertically restricted to the lower 1/2 of the display (V8 = / = V7), and horizontally restricted to the right 1/4 of the display (H8 = 1).

DDFSTRT	49	W	A	Display data fetch start (Horiz. Position)
DDFSTOP	4A	W	A	Display data fetch stop (Horiz. Position)

These registers control the horizontal timing of the beginning and end of the bit-plane DMA display data fetch. The vertical bit-plane DMA timing is identical to the display windows described above. The bit-plane Modulos are dependent on the bit-plane horizontal size, and on the data fetch window size.

BIT #	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
USE	X	X	X	X	X	X	X	X	H8	H7	H6	H5	H4	X	X	X

(X bits should always be driven with 0 to maintain upward compatibility)
The tables below show the start and stop timing for different register contents.

DDFSTRT (Left edge of display data fetch)

PURPOSE	H8	H7	H6	H5	H4
Extra wide (max) *	0	0	1	0	1
wide	0	0	1	1	0
normal	0	0	1	1	1
narrow	0	1	0	0	0

DDFSTOP (Right edge of display data fetch)

PURPOSE	H8	H7	H6	H5	H4
narrow	1	1	0	0	1
normal	1	1	0	1	0
wide (max)	1	1	0	1	1

DMACON	4B	W	A D P	DMA control write (clear or set)
DMACONR	*01	R	A P	DMA control (and Blitter status) read

This register controls all of the DMA channels, and contains Blitter DMA status bits.

BIT #	FUNCTION	DESCRIPTION
15	SET/CLR	Set/Clear control bit. Determines if bits written with a 1 get set or cleared.
14	BBUSY	Blitter busy status bit (read only).
13	BZERO	Blitter logic zero status bit (read only).
12	X
11	X
10	BLTPRI	Blitter DMA priority (over CPU Micro)*
09	DMAEN	Enable all DMA below
08	BPLEN	Bit-plane DMA enable
07	COPEN	Coprocessor DMA enable
06	BLTEN	Blitter DMA enable
05	SPREN	Sprite DMA enable
04	DSKEN	Disk DMA enable
03	AUD3EN	Audio channel 3 DMA enable
02	AUD2EN	Audio channel 2 DMA enable
01	AUD1EN	Audio channel 1 DMA enable
00	AUD0EN	Audio channel 0 DMA enable

• (also called "Blitter Nasty"), (disables /BLS pin, preventing Micro from stealing any bus cycles while Blitter DMA is running)

DSKPTH	+ *10	W	A	Disk pointer (High 3 bits)
DSKPTL	+ *11	W	A	Disk pointer (Low 15 bits)

This pair of registers contain the 18-bit address of Disk DMA data. These address registers must be initialized by the processor or Coprocessor before disk DMA is enabled.

DSKLEN	*12	W	P	Disk length

This register contains the length (number of words) of Disk DMA data. It also contains 2 control bits. These are a DMA enable bit, and a DMA direction (read/write) bit.

BIT #
15	DMAEN	Disk DMA Enable
14	WRITE	Disk Write (RAM to Disk) if 1
13-0	LENGTH	Length (# of words) of DMA data

DSKDAT	& *13	W	P	Disk DMA Data write
DSKDATR	& *04	ER	P	Disk DMA Data read (early read dummy address)

This register is the Disk DMA data buffer. It contains 2 bytes of data that are either sent to (write) or received from (read) the disk. The write mode is enable by bit 14 of the LENGTH register. The DMA controller automatically transfers data to or from this register and RAM, and when the DMA data is finished (Length = 0), it causes a Disk Block Interrupt. See interrupts below.

DSKBYTR	*0D	R	P	Disk Data byte and status read

This register is the Disk Microprocessor data buffer. Data from the disk (in read mode) is loaded into this register one byte at a time, and the Disk Byte Interrupt request bit is set true. This interrupt bit is mirrored in bit 15 of this address to allow simultaneous reading and polling. The interrupt bit must be cleared however by writing to the INTREQ register.

BIT #
15	DSKBYT	Disk byte ready (reset on read)
14	DMAON	(disk)
13	DISKWRITE
12	WORDEQUAL	(from disk sync circuit)
11-08	X	Not used
07-00	DATA	Disk byte data

DSKSYNC	3F	R	P	Disk sync register, holds the code for disk read synchronization. See ADKCON bit 10.
INTREQ	4E	W	P	Interrupt Request bits (clear or set)
INTREQR	*0F	R	P	Interrupt Request bits (read)

This register contains interrupt request bits (or flags). These bits may be polled by the processor, and if enabled by the bits listed in the next register, they may cause processor interrupts. Both a set and clear operation are required to load arbitrary data into this register. The bit assignments are identical to the Enable register below.

INTENA	4D	W	P	Interrupt Enable bits (clear or set bits)
INTENAR	*0E	R	P	Interrupt Enable bits read

This register contains interrupt enable bits. The bit assignments for both the request and enable registers are given below.

BIT #	FUNCT	LEVEL	DESCRIPTION
15	SET/CLR		Set/Clear control bit. Determines if bits written with a 1 get set or cleared. Bits written with a 0 are always unchanged.
14	INTEN		Master interrupt (enable only, no request)
13	EXTER	6	External interrupt
12	DSKBYT	5	Disk Byte ready (disk sync)
11	RBF	5	Serial port Receive Buffer Full
10	AUD3	4	Audio channel 3 block finished
09	AUD2	4	Audio channel 2 block finished
08	AUD1	4	Audio channel 1 block finished
07	AUD0	4	Audio channel 0 block finished
06	BLIT	3	Blitter finished
05	VERTB	3	Start of Vertical blank
04	COPER	3	Coprocessor
03	PORTS	2	I/O Ports and timers
02	OVRUN	1	Serial port receiver overrun
01	DSKBLK	1	Disk Block finished
00	TBE	1	Serial port Transmit Buffer Empty

JOY0DAT	*05	R	D	Joystick-mouse 0 data (left vert, horiz)
JOY1DAT	*06	R	D	Joystick-mouse 1 data (left vert, horiz)

These addresses each read a pair of 8-bit mouse counters. 0 = left controller pair, 1 = right controller pair. (4 counters total). The bit usage for both left and right addresses are shown below. Each counter is clocked by signals from 2 controller pins. Bits 1 and 0 of each counter may be read to determine the state of these 2 clock pins. This allows these pins to double as joystick switch inputs. Mouse counter usage (pins 1-3 = Yclock, pins 2-4 = Xclock)

BIT #	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
0DAT	Y7	Y6	Y5	Y4	Y3	Y2	Y1	Y0	X7	X6	X5	X4	X3	X2	X1	X0
1DAT	Y7	Y6	Y5	Y4	Y3	Y2	Y1	Y0	X7	X6	X5	X4	X3	X2	X1	X0

Joystick switch usage
To detect these read these

Directions	Pin #	Counter Bits
Forward	1	Y1 xor Y0 (BIT# 09 xor BIT# 08)
Left	3	Y1
Back	2	X1 xor X0 (BIT# 01 xor BIT#00)
Right	4	X1

JOYTEST	*1B	W	D	Write to all 4 Joystick-mouse counters at once.

Mouse counter write test data.

BIT #	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
0DAT	Y7	Y6	Y5	Y4	Y3	Y2	xx	xx	X7	X6	X5	X4	X3	X2	X1	X0
1DAT	Y7	Y6	Y5	Y4	Y3	Y2	xx	xx	X7	X6	X5	X4	X3	X2	X1	X0

CONNECTORS	(")	(")	(")	PORTIA
loc.	dir.	sym.	pin	pin
RIGHT	Y	RY	9	33
RIGHT	X	RX	5	32
LEFT	Y	LY	9	36
LEFT	X	LX	5	35

POTGO	*1A	W	P	Pot Port (4-bit) Direction and Data, and Pot Counter start.
POTINP	*0B	R	P	Pot pin data read

This register controls a 4-bit bi-directional I/O port that shares the same 4 pins as the 4 pot counters above.

BIT #	FUNCT	DESCRIPTION
15	OUTRY	Output enable for Portia pin 33
14	DATRY	I/O data Portia pin 33
13	OUTRX	Output enable for Portia pin 32
12	DATRX	I/O data Portia pin 32
11	OUTLY	Output enable for Portia pin 36
10	DATLY	I/O data Portia pin 36
09	OUTLX	Output enable for Portia pin 35
08	DATLX	I/O data Portia pin 35
07-01	X	not used
00	START	Start pots (dump capacitors, start counters)

REFPTR	& *14	W	A	Refresh pointer

This register is used as a Dynamic RAM refresh address generator. It is writable for test purposes only, and should never be written by the microprocessor.

SERDAT	*18	W	P	Serial Port Data and stop bits write

This address writes data to a Transmit data buffer. Data from this buffer is moved into a serial shift register for output transmission whenever it is empty. This sets the Interrupt Request TBE (transmit buffer empty). A stop bit must be provided as part of the data word. The length of the data word is set by the position of the stop bit.

BIT #	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
USE	0	0	0	0	0	0	S	D8	D7	D6	D5	D4	D3	D2	D1	D0

Note S = stop bit = 1, D= data bits

SERDATR	*0C	R	P	Serial Port Data and Status read

This address reads data from a Receive data buffer. Data in this buffer is loaded from a receiving shift register whenever it is full. Several interrupt request bits are also read at this address, along with the data, as shown below.

BIT #
15	OVRUN	Serial port receiver overrun
14	RBF	Serial port Receive Buffer Full (mirror)
13	TBE	Serial port Transmit Buffer Empty (mirror)
12	TSRE	Serial port Transmit shift reg. empty
11	RXD	RXD pin receives UART serial data for direct bit test by the micro
10	x	Not used
09	STP	Stop bit
08	STP-DB8	Stop bit if LONG, Data bit if not
07	DB7	Data bit
06	DB6	Data bit
05	DB5	Data bit
04	DB4	Data bit
03	DB3	Data bit
02	DB2	Data bit
01	DB1	Data bit
00	DB0	Data bit

SERPER	*19	W	P	Serial Port Period and control

This register contains the control bit LONG referred to above, and a 15-bit number defining the serial port Baud Rate. If this number is N, then the Baud Rate is 1 bit every (N+1) * .2794 Microseconds.

BIT #
15	LONG	Defines Serial Receive as 9-bit word.
14-00	RATE	Defines Baud Rate = 1/(N+1) * .2794 microsec.

SPRxPTH	+90	W	A	Sprite x pointer (High 3 bits)
SPRxPTL	+91	W	A	Sprite x pointer (Low 15 bits)

This pair of registers contains the 18-bit address of Sprite x (x = 0, 1, 2, 3, 4, 5, 6, 7) DMA data. These address registers must be initialized by the processor or Coprocessor every vertical blank time.

SPRxPOS	%A0	W	A D	Sprite x Vert-Horiz start position data
SPRxCTL	%A1	W	A D	Sprite x Vert stop position and control data

These 2 registers work together as position, size and feature Sprite control registers. They are usually loaded by the Sprite DMA channel during horizontal blank, however they may be loaded by either processor any time.

SPRxPOS register

BIT #	SYM	FUNCTION
15-08	SV7-SV0	Start vertical value. High bit (SV8) is in SPRxCTL reg below.
07-00	SH8-SH1	Start horizontal value. Low bit (SH0) is in SPRxCTL reg below.

SPRxCTL register (writing this address disables sprite horizontal comparator circuit)

BIT #	SYM	FUNCTION
15-08	EV7-EV0	End (stop) vert value, low 8 bits
07	ATT	Sprite attach control bit (odd sprites)
06-04	X	Not used
02	SVB	Start vert. value high bit
01	EVB	End (stop) vert. value high bit
00	SH0	Start horiz. value low bit

SPRxDATA	%A2	W	D	Sprite x image data register A
SPRxDATB	%A3	W	D	Sprite x image data register B

These registers buffer the Sprite image data. They are usually loaded by the Sprite DMA channel but may be loaded by either processor at any time. When a horizontal comparison occurs, the buffers are dumped into shift registers and serially output to the display, MSB first on the left.

Note Writing to the A buffer enables (arms) the sprite. Writing to the SPRxCTL register disables the sprite. If enabled, data in the A and B buffers will be output whenever the beam counter equals the sprite horizontal position value in the SPRxPOS register.

STREQU	& *1C	S	D	Strobe for horiz sync with VB and EQU
STRVBL	& *1D	S	D	Strobe for horiz sync with VB (Vert. Blank)
STRHOR	& *1E	S	D P	Strobe for horiz sync
STRLONG	& *1F	S	D	Strobe for the identification of long horiz line

One of the first 3 strobe addresses above is places on the dest. addr. bus during the first refresh time slot. The 4th strobe shown above is used during the second refresh time slot of every other line, to identify lines with long counts (228). There are 4 refresh time slots, and any not used for strobes will leave a null (FF) address on the dest. addr. bus.

VPOSR	*02	R	A	Read Vert most sig. bit (and frame flop)
VPOSW	*15	W	A	Write Vert most sig. bit (and frame flop)

BIT#	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
USE	LOF	--	--	--	--	--	--	--	--	--	--	--	--	--	--	V8

LOF = Long frame (auto toggle control bit in BPLCON0)

VHPOSR	*03	R	A	Read Vert and Horiz position of beam
VHPOSW	*16	W	A	Write Vert Vert and Horiz position of beam

BIT#	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
USE	V7	V6	V5	V4	V3	V2	V1	V0	H8	H7	H6	H5	H4	H3	H2	H1

RESOLUTION = 1/160 OF SCREEN WIDTH (280 NS)

Appendix B - REGISTER NAMES

APPENDIX B - Commodore-Amiga PC Hardware Manual

THIS IS THE SYSTEM FILE NAMED "REGNAME".
It is generated and maintained by Commodore-Amiga Hardware Engineering.

custom IC register allocation
preliminary	8/04/83	rhn
revised	8/16/83	jgm
revised	8/18/83	jgm
revised	8/23/83	jgm
revised	9/01/83	jgm
revised	9/16/83	jgm
revised	9/19/83	jgm
revised	9/26/83	jgm
revised	10/27/83	jgm
revised REGNAM.9	11/19/83	jgm
revised REGNAME	11/29/83	jgm

& = Register used by DMA channel only.

% = Register used by DMA channel usually, processors sometimes.

+ = Address register pair. Low word uses DB1-DB15, High word DB0-DB2

• = Address not writable by the Coprocessor.
  

~ = Address not writable by the Coprocessor unless COPCON is set true.

A = Agnus chip, D = Daphne chip, P = Portia chip

W = Write, R = Read

ER = Early Read. This is a DMA data transfer to RAM, from either the Disk or from the Blitter. RAM timing requires data to be on the bus earlier than microprocessor read cycles. These transfers are therefore initiated by Agnus timing, rather than a read address on the dest. adr. bus.

S = Strobe (write address with no register bits

PTL, PTH = 18-bit Pointer that addresses DMA data. Must be reloaded by a processor before use (Vertical blank for Bit-plane and Sprite pointers, and prior to starting the Blitter for Blitter pointers).

LCL, LCH - 18-bit Location (starting address) of DMA data. Used to automatically restart pointers, such as the Coprocessor program counter (during vertical blank), and the Audio sample counter (whenever the audio length count is finished).

MOD = 15-bit Modulo. A number that is automatically added to the memory address at the end of each line to generate the address for the beginning of the next line. This allows the Blitter (or the Display Window) to operate on (or display) a window of data that is smaller than the actual picture in memory, (memory map) uses 15 bits, plus sign extend.

NAME	ADD	R/W	CHIP	FUNCTION
BLTDDAT	& *00	ER	A	Blitter dest. early read (dummy address)
DMACONR	*01	R	A P	DMA control (and Blitter status) read
VPOSR	*02	R	A	Read Vert most sig. bit (and frame flop)
VHPOSR	*03	R	A	Read Vert and Horiz position of beam
DSKDATR	& *04	ER	P	Disk data early read (dummy address)
JOY0DAT	*05	R	D	Joystick-mouse 0 data (vert, horiz)
JOY1DAT	*06	R	D	Joystick-mouse 1 data (vert, horiz)
CLXDAT	*07	R	D	Collision data reg. (read and clear)
ADKCONR	*08	R	P	Audio, disk control register read
POT0DAT	*09	R	P	Pot counter pair 0 data (vert, horiz)
POT1DAT	*0A	R	P	Pot counter pair 1 data (vert, horiz)
POTINP	*0B	R	P	Pot pin data read
SERDATR	*0C	R	P	Serial Port Data and status read
DSKBYTR	*0D	R	P	Disk Data byte and status read
INTENAR	*0E	R	P	Interrupt Enable bits read
INTREQR	*0F	R	P	Interrupt request bits read
DSKPTH	+ *10	W	A	Disk pointer (High 3 bits)
DSKPTL	+ *11	W	A	Disk pointer (Low 15 bits)
DSKLEN	*12	W	P	Disk length
DSKDAT	& *13	W	P	Disk DMA Data write
REFPTR	& *14	W	A	Refresh pointer
VPOSW	*15	W	A	Write Vert most sig. bit (and frame flop)
VHPOSW	*16	W	A	Write Vert and horiz position of beam
COPCON	*17	W	A	Coprocessor control register (CDANG)
SERDAT	*18	W	P	Serial Port Data and stop bits write
SERPER	*19	W	P	Serial Port Period and control
POTGO	*1A	W	P	Pot count start, pot pin drive enable and data
JOYTEST	*1B	W	D	Write to all 4 Joystick-mouse counters at once
STREQU	& *1C	W	D	Strobe for horiz sync with VB and EQU
STRVBL	& *1D	W	D	Strobe for horiz sync with VB (Vert. Blank)
STRHOR	& *1E	W	D P	Strobe for horiz sync
STRLONG	& *1F	W	D	Strobe for identification of long horiz. line
BLTCON0	~20	W	A	Blitter control register 0
BLTCON1	~21	W	A	Blitter control register 1
BLTAFWM	~22	W	A	Blitter first word mask for source A
BLTALWM	~23	W	A	Blitter last word mask for source A
BLTCPTH	+ ~24	W	A	Blitter Pointer to source C (High 3 bits)
BLTCPTL	+ ~25	W	A	Blitter Pointer to source C (Low 15 bits)
BLTBPTH	+ ~26	W	A	Blitter Pointer to source B (High 3 bits)
BLTBPTL	+ ~27	W	A	Blitter Pointer to source B (Low 15 bits)
BLTAPTH	+ ~28	W	A	Blitter Pointer to source A (High 3 bits)
BLTAPTL	+ ~29	W	A	Blitter Pointer to source A (Low 15 bits)
BLTDPTH	+ ~2A	W	A	Blitter Pointer to source D (High 3 bits)
BLTDPTL	+ ~2B	W	A	Blitter Pointer to source D (Low 15 bits)
BLTSIZE	+ ~2C	W	A	Blitter Pointer to destn. D (High 3 bits)
	~2D
	~2E
	~2F
BLTCMOD	~30	W	A
BLTBMOD	~31	W	A
BLTAMOD	~32	W	A
BLTDMOD	~33	W	A
	~34
	~35
	~36
	~37
BLTCDAT	~38	W	A
BLTBDAT	~39	W	A
BLTADAT	~3A	W	A
	~3B
	~3C
	~3D
	~3E
DSKSYN	~3F	W	P	Disk sync pattern register for disk read
COP1LCH	+40	W	A	Coprocessor first location reg (High 3 bits)
COP1LCL	+41	W	A	Coprocessor first location reg (Low 15 bits)
COP2LCH	+42	W	A	Coprocessor second location reg (High 3 bits)
COP2LCL	+43	W	A	Coprocessor second location reg (Low 15 bits)
COPJMP1	44	S	A	Coprocessor restart at first location
COPJMP2	45	S	A	Coprocessor restart at second location
COPINS	46	W	A	Coprocessor inst. fetch identify
DIWSTRT	47	W	A	Display Window Start (upper left vert-hor pos)
DIWSTOP	48	W	A	Display Window Stop (lower right vert-hor pos)
DDFSTRT	49	W	A	Display bit-plane data fetch start (hor pos)
DDFSTOP	4A	W	A	Display bit-plane data fetch stop (hor pos)
DMACON	4B	W	A D P	DMA control write (clear or set)
CLXCON	4C	W	D	Collision control
INTENA	4D	W	P	Interrupt Enable bits (clear or set bits)
INTREQ	4E	W	P	Interrupt Request bits (clear or set bits)
ADKCON	4F	W	P	Audio, Disk control
AUD0LCH	+50	W	A	Audio channel 0 location (High 3 bits)
AUD0LCL	+51	W	A	Audio channel 0 location (Low 15 bits)
AUD0LEN	52	W	P	Audio channel 0 length
AUD0PER	53	W	P	Audio channel 0 period
AUD0VOL	54	W	P	Audio channel 0 volume
AUD0DAT	&55	W	P	Audio channel 0 data
	56
	57
AUD1LCH	+58	W	A	Audio channel 1 location (High 3 bits)
AUD1LCL	+59	W	A	Audio channel 1 location (Low 15 bits)
AUD1LEN	5A	W	P	Audio channel 1 length
AUD1PER	5B	W	P	Audio channel 1 period
AUD1VOL	5C	W	P	Audio channel 1 volume
AUD1DAT	&5D	W	P	Audio channel 1 data
	5E
	5F
AUD2LCH	+60	W	A	Audio channel 2 location (High 3 bits)
AUD2LCL	+61	W	A	Audio channel 2 location (Low 15 bits)
AUD2LEN	62	W	P	Audio channel 2 length
AUD2PER	63	W	P	Audio channel 2 period
AUD2VOL	64	W	P	Audio channel 2 volume
AUD2DAT	&65	W	P	Audio channel 2 data
	66
	67
AUD3LCH	+68	W	A	Audio channel 3 location (High 3 bits)
AUD3LCL	+69	W	A	Audio channel 3 location (High 3 bits)
AUD3LEN	6A	W	P	Audio channel 3 length
AUD3PER	6B	W	P	Audio channel 3 period
AUD3VOL	6C	W	P	Audio channel 3 volume
AUD3DAT	&6D	W	P	Audio channel 3 data
	6E
	6F
BPL1PTH	+70	W	A	Bit-plane 1 pointer (High 3 bits)
BPL1PTL	+71	W	A	Bit-plane 1 pointer (Low 15 bits)
BPL2PTH	+72	W	A	Bit-plane 2 pointer (High 3 bits)
BPL2PTL	+73	W	A	Bit-plane 2 pointer (Low 15 bits)
BPL3PTH	+74	W	Example	Bit-plane 3 pointer (High 3 bits)
BPL3PTL	+75	W	Example	Bit-plane 3 pointer (Low 15 bits)
BPL4PTH	+76	W	Example	Bit-plane 4 pointer (High 3 bits)
BPL4PTL	+77	W	Example	Bit-plane 4 pointer (Low 15 bits)
BPL5PTH	+78	W	Example	Bit-plane 5 pointer (High 3 bits)
BPL5PTL	+79	W	Example	Bit-plane 5 pointer (Low 15 bits)
BPL6PTH	+7A	W	Example	Bit-plane 6 pointer (High 3 bits)
BPL6PTL	+7B	W	Example	Bit-plane 6 pointer (Low 15 bits)
	7C
	7D
	7E
	7F
BPLCON0	80	W	A D	Bit-plane control register (misc. control bits)
BPLCON1	81	W	D	Bit-plane control register (scroll value PF1, PF2)
BPLCON2	82	W	D	Bit-plane control register (priority control)
	83
BPL1MOD	84	W	A	Bit-plane Modulo (odd planes)
BPL2MOD	85	W	A	Bit-plane Modulo (even planes)
	86
	87
BPL1DAT	&88	W	D	Bit-plane 1 data (parallel to serial convert)
BPL2DAT	&89	W	D	Bit-plane 2 data (parallel to serial convert)
BPL3DAT	&8A	W	D	Bit-plane 3 data (parallel to serial convert)
BPL4DAT	&8B	W	D	Bit-plane 4 data (parallel to serial convert)
BPL5DAT	&8C	W	D	Bit-plane 5 data (parallel to serial convert)
BPL6DAT	&8D	W	D	Bit-plane 6 data (parallel to serial convert)
	8E
	8F
SPR0PTH	+90	W	A	Sprite 0 pointer (High 3 bits)
SPR0PTL	+91	W	A	Sprite 0 pointer (Low 15 bits)
SPR1PTH	+92	W	A	Sprite 1 pointer (High 3 bits)
SPR1PTL	+93	W	A	Sprite 1 pointer (Low 15 bits)
SPR2PTH	+94	W	A	Sprite 2 pointer (High 3 bits)
SPR2PTL	+95	W	A	Sprite 2 pointer (Low 15 bits)
SPR3PTH	+96	W	A	Sprite 3 pointer (High 3 bits)
SPR3PTL	+97	W	A	Sprite 3 pointer (Low 15 bits)
SPR4PTH	+98	W	A	Sprite 4 pointer (High 3 bits)
SPR4PTL	+99	W	A	Sprite 4 pointer (Low 15 bits)
SPR5PTH	+9A	W	A	Sprite 5 pointer (High 3 bits)
SPR5PTL	+9B	W	A	Sprite 5 pointer (Low 15 bits)
SPR6PTH	+9C	W	A	Sprite 6 pointer (High 3 bits)
SPR6PTL	+9D	W	A	Sprite 6 pointer (Low 15 bits)
SPR7PTH	+9E	W	A	Sprite 7 pointer (High 3 bits)
SPR7PTL	+9F	W	A	Sprite 7 pointer (Low 15 bits)
SPR0POS	%A0	W	A D	Sprite 0 Vert-Horiz start position data
SPR0CTL	%A1	W	A D	Sprite 0 Vert stop position and control data
SPR0DATA	%A2	W	D	Sprite 0 image data register A
SPR0DATB	%A3	W	D	Sprite 0 image data register B
SPR1POS	%A4	W	A D	Sprite 1 Vert-Horiz start position data
SPR1CTL	%A5	W	A D	Sprite 1 Vert stop position and control data
SPR1DATA	%A6	W	D	Sprite 1 image data register A
SPR1DATB	%A7	W	D	Sprite 1 image data register B
SPR2POS	%A8	W	A D	Sprite 2 Vert-Horiz start position data
SPR2CTL	%A9	W	A D	Sprite 2 Vert stop position and control data
SPR2DATA	%AA	W	D	Sprite 2 image data register A
SPR2DATB	%AB	W	D	Sprite 2 image data register B
SPR3POS	%AC	W	A D	Sprite 3 Vert-Horiz start position data
SPR3CTL	%AD	W	A D	Sprite 3 Vert stop position and control data
SPR3DATA	%AE	W	D	Sprite 3 image data register A
SPR3DATB	%AF	W	D	Sprite 3 image data register B
SPR4POS	%B0	W	A D	Sprite 4 Vert-Horiz start position data
SPR4CTL	%B1	W	A D	Sprite 4 Vert stop position and control data
SPR4DATA	%B2	W	D	Sprite 4 image data register A
SPR4DATB	%B3	W	D	Sprite 4 image data register B
SPR5POS	%B4	W	A D	Sprite 5 Vert-Horiz start position data
SPR5CTL	%B5	W	A D	Sprite 5 Vert stop position and control data
SPR5DATA	%B6	W	D	Sprite 5 image data register A
SPR5DATB	%B7	W	D	Sprite 5 image data register B
SPR6POS	%B8	W	A D	Sprite 6 Vert-Horiz start position data
SPR6CTL	%B9	W	A D	Sprite 6 Vert stop position and control data
SPR6DATA	%BA	W	D	Sprite 6 image data register A
SPR6DATB	%BB	W	D	Sprite 6 image data register B
SPR7POS	%BC	W	A D	Sprite 7 Vert-Horiz start position data
SPR7CTL	%BD	W	A D	Sprite 7 Vert stop position and control data
SPR7DATA	%BE	W	D	Sprite 7 image data register A
SPR7DATB	%BF	W	D	Sprite 7 image data register B
COLOR00	C0	W	D	Color table 00
COLOR01	C1	W	D	Color table 01
COLOR02	C2	W	D	Color table 02
COLOR03	C3	W	D	Color table 03
COLOR04	C4	W	D	Color table 04
COLOR05	C5	W	D	Color table 05
COLOR06	C6	W	D	Color table 06
COLOR07	C7	W	D	Color table 07
COLOR08	C8	W	D	Color table 08
COLOR09	C9	W	D	Color table 09
COLOR10	CA	W	D	Color table 10
COLOR11	CB	W	D	Color table 11
COLOR12	CC	W	D	Color table 12
COLOR13	CD	W	D	Color table 13
COLOR14	CE	W	D	Color table 14
COLOR15	CF	W	D	Color table 15
COLOR16	D0	W	D	Color table 16
COLOR17	D1	W	D	Color table 17
COLOR18	D2	W	D	Color table 18
COLOR19	D3	W	D	Color table 19
COLOR20	D4	W	D	Color table 20
COLOR21	D5	W	D	Color table 21
COLOR22	D6	W	D	Color table 22
COLOR23	D7	W	D	Color table 23
COLOR24	D8	W	D	Color table 24
COLOR25	D9	W	D	Color table 25
COLOR26	DA	W	D	Color table 26
COLOR27	DB	W	D	Color table 27
COLOR28	DC	W	D	Color table 28
COLOR29	DD	W	D	Color table 29
COLOR30	DE	W	D	Color table 30
COLOR31	DF	W	D	Color table 31
RESERVED	EX
RESERVED	FX
NO-OP (NULL)	FF